The semiconductor elements manufactured by using a semiconductor integrated circuit technology are processed as described in JP-A-8-162512. Namely, the semiconductor elements are examined (on-wafer tested) in the stage those are fabricated on a semiconductor wafer. Then, the semiconductor wafer is diced into individual pieces of semiconductor elements, which are again tested (finally tested) in the stage where the semiconductor elements are respectively assembled in packages. In accordance with the result of the final test, the semiconductor devices (packaged semiconductor elements) are graded.
This is the same case as in the solid-state imaging element. Namely, as shown in FIG. 2, after a plurality of solid-state imaging elements are fabricated on a semiconductor wafer (step S1), an on-wafer test is conducted (step S2) to thereby examine the individual solid-state imaging elements on the wafer. Then, the semiconductor wafer is diced into individual pieces of solid-state imaging elements. The solid-state imaging elements, only which have been determined acceptable in the wafer test, are respectively encapsulated in ceramic packages (step S4), to again conduct an examination (final test) on the solid-state imaging devices (the packaged solid-state imaging elements) (step S5). In accordance with the result of the final test, the solid-state imaging devices are graded (step S6).
In the case of manufacturing a semiconductor device, final test is conducted in addition to on-wafer test. It is a usual practice to implement a grading of semiconductor devices, such as memories or CPUs, based upon the operation speed thereof The semiconductor device, if operable higher in speed, is graded higher.
Contrary to this, it is impossible to grade solid-state imaging devices. A variety of test data is required. For example, the solid-state imaging device, if less in pixel defects, is higher in grade. However, when the solid-state imaging device is illuminated with examination light during testing, if there is no occurrence of shading, then it is determined high in grade. In case shading occurs, it is low in grade even if less in pixel defects.
In this manner, grading of solid-state imaging devices is not simple but a broad range of data is required for grading. The number of items for testing the solid-sate imaging devices is greater as compared to that of the semiconductor devices, such as memories. This requires a longer time in the test process correspondingly. Moreover, because of the requirement of twice tests, i.e. on-wafer and final tests, the time required in the test process problematically increases manufacturing cost.